Method of manufacturing leadframes for semiconductor devices, corresponding leadframe and semiconductor device

ABSTRACT

Leadframes for semiconductor devices are manufactured by providing a laminar substrate of laser direct structuring material, the laminar substrate comprising first and second opposed surfaces, applying laser beam processing to the substrate to provide a first pattern of electrically-conductive formations at the first surface, a second pattern of electrically-conductive formations at the second surface and electrically-conductive vias through the substrate between the first surface and the second surface. Electrically-conductive material is formed, for instance via electrolytic or electroless growth of electrically-conductive material such a copper onto the first and second pattern of electrically-conductive formations as well as onto the electrically-conductive vias provided by applying laser beam processing to the substrate. The electrically-conductive vias are coupled to one or both of the electrically-conductive formations in the first pattern of electrically-conductive formations and the second pattern of electrically-conductive formations.

BACKGROUND Technical Field

The description relates to manufacturing semiconductor devices.

One or more embodiments may be applied to manufacturing leadframes forsemiconductor devices such as integrated circuits (ICs), for instance.

Description of the Related Art

Various technologies are currently available for manufacturingleadframes/substrates for various types of semiconductor devices such asQFN (Quad Flat No-lead), LGA (Land Grid Array), BGA (Ball Grid Array)semiconductor devices.

So-called “coreless” leadframe technology facilitates using a leadframeas it is, that is without tape support.

Solutions currently referred to as MIS (Molded Interconnect Solutions)are exemplary of devices to which coreless leadframe technology mayapply.

Essentially, MIS is a leadframe manufacturing technology similar to BGAlaminate technology using a molding compound as the core.

Such a technology facilitates achieving fine inner lead tip pitch (50/60micron, for instance) which is highly desirable for flip-chipapplications.

It is noted that such arrangements may exhibit relatively low yield atmanufacturing with costs of about 50-100% in excess of “standard” tapedleadframes.

Additionally, certain conventional solutions may exhibit drawbacksrelated, for instance, to possible warpage (in the case of a metalcarrier and a film mold, for instance).

In the case of MIS technology, notable leadframe warpage may be observedafter assembly steps involving a thermal budget such as, for instance:

-   -   die attachment with Die Attach Film (DAF): 100° C., few seconds;    -   die attachment with glue/DAF curing 190° C., 1.5 hours;    -   wire bonding (WB): 180-220° C., from few seconds to several        minutes;    -   (package) molding: 175° C., from 40 to 200 seconds; and    -   Post Mold Curing: 175° C., from 4 to 12 hours.

BRIEF SUMMARY

The present disclosure provides one or more embodiments that overcomethe drawbacks discussed in the foregoing.

According to one or more embodiments, such drawbacks can be overcome byresorting to a method having the features set forth in the claims thatfollow.

One or more embodiments may relate to a corresponding leadframe.

One or more embodiments may relate to a corresponding device (anintegrated circuit, for instance).

The claims are an integral part of the technical disclosure ofembodiments as provided herein.

One or more embodiments may offer one or more of the followingadvantages:

-   -   simplified processing, which facilitates avoiding acts such as        metal (copper) lamination, resist lamination, resist exposure,        metal etching, resist stripping;    -   possible implementation within an IC manufacturing plant (back        end);    -   reduced cycle time for prototypes; and    -   reduced cost.

One or more embodiments may use laser direct structuring (LDS)technology in order to create vias and lines with the capability ofreplacing a metallic frame by metallization of vias and lines.

In at least one embodiment, a method of manufacturing leadframes forsemiconductor devices is provided that includes: forming, by laser beamprocessing, a first pattern of electrically-conductive structures at afirst surface of a laminar substrate; forming, by the laser beamprocessing, a second pattern of electrically-conductive structures at asecond surface of the substrate, the second surface being opposite thefirst surface; and forming electrically-conductive vias through thesubstrate between the first surface of the substrate and the secondsurface of the substrate, the electrically-conductive vias coupled to atleast one of the electrically-conductive structures in the first patternof electrically-conductive structures and in the second pattern ofelectrically-conductive structures.

In at least one embodiment, a leadframe for semiconductor devices isprovided that includes a laminar substrate of laser direct structuringmaterial, the laminar substrate having first and second opposedsurfaces. A first pattern of electrically-conductive structures isdisposed at the first surface of the substrate, and the first pattern ofelectrically-conductive structures is formed by laser beam processing. Asecond pattern of electrically-conductive structures is disposed at thesecond surface of the substrate, and the second pattern ofelectrically-conductive structures is formed by laser beam processing.Electrically-conductive vias extend through the substrate between thefirst surface of the substrate and the second surface of the substrate,and the electrically-conductive vias are coupled to at least one of theelectrically-conductive structures in the first pattern ofelectrically-conductive structures and in the second pattern ofelectrically-conductive structures.

In at least one embodiment, a semiconductor device is provided thatincludes a leadframe and at least one semiconductor chip or die attachedto the leadframe. The leadframe includes: a laminar substrate of laserdirect structuring material, the laminar substrate having first andsecond opposed surfaces; a first pattern of electrically-conductivestructures at the first surface of the substrate, the first pattern ofelectrically-conductive structures formed by laser beam processing; asecond pattern of electrically-conductive structures at the secondsurface of the substrate, the second pattern of electrically-conductivestructures formed by laser beam processing; and electrically-conductivevias extending through the substrate between the first surface of thesubstrate and the second surface of the substrate, theelectrically-conductive vias coupled to at least one of theelectrically-conductive structures in the first pattern ofelectrically-conductive structures and in the second pattern ofelectrically-conductive structures. The at least one semiconductor chipor die is electrically coupled to the first pattern ofelectrically-conductive formations at the first surface of thesubstrate, the second pattern of electrically-conductive formations atthe second surface of the substrate and the electrically-conductivevias.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

One or more embodiments will now be described, by way of example only,with reference to the annexed figures, wherein:

FIGS. 1A to 1G are cross-sectional diagrams illustrating a method ofmaking or producing a leadframe in accordance with some embodiments;

FIG. 2 is a plan view illustrating a leadframe in accordance with someembodiments;

FIG. 3 is a plan view illustrating the leadframe of FIG. 2 from aviewpoint opposite the viewpoint of FIG. 2 ;

FIGS. 4A and 4B are cross-sectional diagrams illustrating possible typesof substrates which may be utilized in accordance with some embodiments;and

FIG. 5 is plan view illustrating a leadframe in accordance with someembodiments.

It will be appreciated that, for the sake of clarity and ease ofrepresentation, the various figures may not be drawn to a same scale.

DETAILED DESCRIPTION

In the ensuing description, one or more specific details areillustrated, aimed at providing an in-depth understanding of examples ofembodiments of this description. The embodiments may be obtained withoutone or more of the specific details, or with other methods, components,materials, etc. In other cases, known structures, materials, oroperations are not illustrated or described in detail so that certainaspects of embodiments will not be obscured.

Reference to “an embodiment” or “one embodiment” in the framework of thepresent description is intended to indicate that a particularconfiguration, structure, or characteristic described in relation to theembodiment is comprised in at least one embodiment. Hence, phrases suchas “in an embodiment” or “in one embodiment” that may be present in oneor more points of the present description do not necessarily refer toone and the same embodiment. Moreover, particular conformations,structures, or characteristics may be combined in any adequate way inone or more embodiments.

The references used herein are provided merely for convenience and hencedo not define the extent of protection or the scope of the embodiments.

The designation “leadframe” (or “lead frame”) is currently used (see forinstance the USPC Consolidated Glossary of the United States Patent andTrademark Office) to indicate a metal frame which provides support foran integrated circuit chip or die as well as electrical leads tointerconnect the integrated circuit in the die or chip to otherelectrical components or contacts.

Laser Direct Structuring (LDS) is a laser-based machining technique nowwidely used in various sectors of the industrial and consumerelectronics markets, for instance for high-performance antennaintegration, where an antenna design can be directly formed onto amolded plastic part.

In an exemplary process, molded parts can be produced with commerciallyavailable resins which include additives suitable for the LDS process; abroad range of resins such as polymer resins like polycarbonate (PC),polycarbonate/acrylonitrile butadiene styrene (PC/ABS), acrylonitrilebutadiene styrene (ABS), liquid-crystal polymer (LCP) are currentlyavailable for that purpose.

In LDS, a laser beam can be used to transfer a desiredelectrically-conductive pattern on the plastic molding, which is thensubjected to metallization (for instance via electroless plating withcopper or other metals) to finalize the desired conductive pattern.

One or more embodiments as exemplified herein involve the recognitionthat LDS facilitates providing electrically-conductive formations suchas vias and lines in a molding compound, without further manufacturingsteps and with a high flexibility in the shapes which can be obtained.

One or more embodiments can be applied to various types of semiconductordevices such as (by way of non-limiting examples) those semiconductordevices currently referred to as a QFN or QFN-mr, these being acronymsfor Quad Flat Pack No-lead and Multirow Quad Flat Pack No-lead.

Such devices may include leadframes with so-called routed leads, namelyelectrically-conductive formations (leads) which from an outlinelocation extend inwardly in the direction of a semiconductor chip ordie.

One or more embodiments may facilitate achieving a reduced (fine) leadtip pitch at the inner (proximal) ends of the leads, that is the ends ofthe leads towards the semiconductor chip.

FIGS. 1A to 1G are cross-sectional diagrams illustrating a method ofmaking or producing a leadframe (for instance for any one of the varioustypes of semiconductor devices discussed in the foregoing) using LDStechnology, in accordance with one or more embodiments.

FIG. 1A is exemplary of forming a substrate or layer 10 (a laminatecore, for instance) of LDS material.

Any known LDS material (such as, for instance, a polymer resin like PC,PC/ABS, ABS, LCP including additives suitable for the LDS process) maybe used advantageously in embodiments.

FIG. 1B is exemplary of an act of structuring the substrate 10 of FIG.1A at the “bottom” or “back” surface thereof, designated 10 a.

Such structuring may involve forming by LDS processing (that is, laserbeam machining as schematically indicated at L) a first pattern ofelectrically-conductive structures or formations 12, 120.

FIG. 1C is exemplary of an act of structuring the substrate 10 of FIGS.1A and 10B at the “top” or “front” surface thereof, designated 10 b.

Such structuring (possibly, but not necessarily, performed afteroverturning the substrate 10) may involve forming, again by LDSprocessing (that is, laser beam machining L), a second pattern ofelectrically-conductive structures or formations 14, 140.

Those of skill in the art will appreciate that both the first patternand the second pattern of electrically-conductive formations 12, 120 and14, 140 can be provided according to any of a virtually boundlessvariety of possible patterns as desired, by also taking advantage of theintrinsic flexibility of LDS laser beam processing.

For instance, FIGS. 2 and 3 are exemplary of embodiments of performingthe acts of FIG. 1A to 1F on strip-like material, virtually ofindefinite length, to provide (simultaneously) a plurality of leadframes with longitudinal electrically-conductive formations 120, 140extending along the sides of the strip-like material.

FIG. 1D is exemplary of laser processing (drilling by laser beam L) thesubstrate 10 having the front and back surfaces 10 a, 10 b structured asdiscussed previously to open vias 16 extending at desired locationsbetween the electrically-conductive formations of the two patterns 12,14 over the two surfaces 10 a, 10 b.

FIG. 1E is exemplary of similar processing (e.g., laser drilling)possibly applied to the structure of FIG. 1D in those embodiments where,as exemplified in FIGS. 2 and 3 , the acts of FIGS. 1A to 1G areperformed on strip-like material, to provide indexing holes 18(essentially openings at a given pitch) in the longitudinalelectrically-conductive formations 120, 140 or “rails” extending alongthe sides of the strip-like material.

FIG. 1F is exemplary of embodiments of growing conductive material(metal such as copper—Cu, for instance) onto the structured pathsprovided via laser processing of the LDS material as exemplified inFIGS. 1B to 1E.

Electroless/electrolytic growth as exemplified by EE in FIG. 1F may beused for that purpose, that is in order to improve (via growth ofcopper, for instance) the conductivity of the traces/holes formed in theLDS material by laser processing.

Electroless processing (optionally preceding electrolytic processing)may facilitate a thicker metal growth.

Also, in those embodiments where a high (Cu, for instance) metal growthis not a desired feature, electroless alone (that is withoutelectrolytic plating) can be used.

It is noted that the conductive formations (traces, for instance) formedwith laser processing of LDS material may have a thickness, and thus aconductivity, insufficient for certain applications, such as powerdevices, for instance: indeed few microns of LDS material may be ablatedin the laser activation process (and possibly more in the case ofdrilling), with the treated material possibly having activated particles(chromium, for instance) at its surface.

Also, while exemplified in relief in the figures for simplicity and easeof understanding, the laser-treated surface portions of the LDS materialmay not be in relief, but rather recessed.

Those of skill in the art will thus appreciate that passing from an“intermediate” structure obtained (solely) via laser activation to aresulting final structure may involve such a step as exemplified in FIG.1F, that is forming, e.g., electroplated conductive formations.

FIG. 1G is exemplary of an (optional) plating act PT which may beapplied with otherwise conventional means in order to provide platedconductive formations over the leads at the bottom side 10 a and/or overthe lead tips at the top side 10 b: see, for instance 12′ (materialcomplying with surface mount soldering, for instance) and 1400 (thesemay be pads or bumps for wire/ribbon bonding or the like) in FIG. 1G.

Figures from 1A to 1G are thus exemplary of a manufacturing sequence ofan exemplary leadframe including acts of: strip molding (FIG. 1A),bottom laser structuring (FIG. 1B), top laser structuring (FIG. 1C),vias generation connecting the two top/bottom layers (FIG. 1D), openingof indexing holes (or any other feature as desired) on top/bottom rails(FIG. 1E), forming conductive material onto the traces, holes, and so onobtained by laser structuring (FIG. 1F), top/bottom layer metallization(FIG. 1G).

For instance, in an act as exemplified in FIG. 1F, all traces, holesobtained by laser structuring (see FIGS. 1B to 1E, for example) may beelectroless plated—for less than 10 micron thickness, for instance—orelectroplated—up to 50 microns thickness—in case of high currentdevices, for instance.

FIGS. 2 and 3 are exemplary of a device or structure resulting from themethod illustrated in FIGS. 1A to 1G in a plan view from the top orfront side 10 b (FIG. 2 ) and from the bottom or back surface 10 a (FIG.3 ).

As discussed, FIGS. 2 and 3 are exemplary of a device or structureresulting from performance of the method of FIG. 1A to 1F on strip-likematerial, virtually of indefinite length, to provide a plurality of leadframes to be finally “singulated” (before or after die attachment).

Such an act of singulation may be facilitated by using the indexingholes 18 in the longitudinal electrically-conductive formations 120, 140or “rails”.

Indeed, such leadframe rails 120, 140 may contain features (such asholes 18) which facilitate leadframe indexing and/or unit location intoassembly equipment. They can also contain identification codes (2DCodes) and “fiducials” (such as crosses, L shapes, or the like) whichfacilitates properly locating the path of the sawing blade duringpackage singulation.

FIGS. 4A and 4B are exemplary of applying processing as discussed inconnection with the previous figures both to “mono-thickness” substrates10 and to “dual-thickness” or “multiple-thickness” substrates, forinstance having a mesa-like cross sectional profile with a centralportion upstanding in comparison with the longitudinal sides of thestrip-like structure exemplified in FIGS. 2 and 3 . One or moreembodiments as exemplified herein may thus apply to device structurebased on a copper dual layer or multiple layers.

FIG. 5 is exemplary of a leadframe adapted to be produced as exemplifiedherein. A single leadframe is exemplified for simplicity showing thepresence of a (central) die-mounting area at the top or front surface 10b where a semiconductor die or chip can be attached (by any techniqueknown for that purpose to those of skill in the art as discussed by wayof example in the introductory portion of the description) as indicatedin dashed lines at C.

As exemplified in FIG. 5 , the pattern of electrically-conductiveformations 14 may provide an array of routing leads suited to provideelectrical coupling of the semiconductor die or chip with contact padsaccessible from outside a device package. A possible outline of such apackage (which may be provided by any technique known for that purposeto those of skill in the art, for instance by molding an epoxy moldingcompound) is indicated by P in FIG. 5 .

Electrical coupling of the semiconductor die or chip may be viaconventional techniques such as wire bonding, stud bumps or the like.

Whatever the option(s) adopted for that purpose, such coupling may takeadvantage of the provision of contact formations as indicated by 1400 inFIG. 5 .

FIG. 5 also exemplifies the possible presence of contact lands or bumpsas indicated by 1400′ which do not come down to anyelectrically-conductive formations 14 at the top or front surface 10 bbut rather correspond to vias 16 formed through the substrate 10 comingdown to electrically-conductive formations 12 at the bottom or backsurface 10 a.

One or more embodiments as exemplified herein thus adopt laser directstructuring (LDS) processing in order to create electrically-conductiveformations such as vias and lines of various types with metallization ofvias and lines adapted to replace a metallic frame.

FIG. 5 is exemplary of a “real-world” example providing a leadframeincluding an array of leads extending between a die-mounting region formounting a semiconductor chip or die C and the periphery of a substrate10 of an LDS material. As exemplified in FIG. 5 , one or more of theseleads may have a generally flared shape with a narrow “proximal” tipfacing the die mounting area C and a width (and thusarea/cross-sectional area) gradually increasing in a “distal” directionaway from the die mounting area towards for periphery of the substrate10.

As noted, final singulation of a lead frame (as exemplified by arrows Sin FIG. 5 ) may take place with the die or chip C already attachedthereon, possibly with die or chip already electrically coupled andpackaged as discussed previously.

One or more embodiments facilitate providing a device structure with orwithout plated conductive formations (die pads, for instance) on bothsides of the leadframe.

One or more embodiments may adopt LDS structuring in order to createelectrically-conductive formations such as vias and lines withmetallization of vias and lines adapted to replace a metallic frame suchas conventional leadframes.

A method of manufacturing leadframes for semiconductor devices asexemplified herein may comprise:

providing a laminar substrate (for instance, 10) of laser directstructuring material, the laminar substrate comprising first (forinstance, bottom or back surface 10 a) and second (for instance, top orfront surface 10 b) opposed surfaces; and applying laser beam processing(for instance, L) to said substrate to provide a first pattern ofelectrically-conductive formations (for instance, 12, 120) at the firstsurface of said substrate, a second pattern of electrically-conductiveformations (for instance, 14, 140) at the second surface of saidsubstrate, and electrically-conductive vias (for instance, 16) throughsaid substrate between the first surface of said substrate (10) and thesecond surface of said substrate, the electrically-conductive viascoupled to at least one (that is, to both of 12, 14, see, for instance12, 14 in FIG. 1D to 1G or even just one, see, for instance and 1400′ inFIG. 5 , where 1400′ are coupled only to 12 on the bottom of back side)of the electrically-conductive formations in said first pattern ofelectrically-conductive formations and said second pattern ofelectrically-conductive formations.

A method as exemplified herein may comprise applying laser beamprocessing to said substrate to provide electrically-conductive viascoupled to at least one of the electrically-conductive formations insaid first pattern of electrically-conductive formations and at leastone of the electrically-conductive formations in said second pattern ofelectrically-conductive formations (see, for instance 16 in FIGS. 1D to1G).

A method as exemplified herein may comprise forming (see EE in FIG. 1F,for instance) electrically-conductive material onto said first patternof electrically-conductive formations, said second pattern ofelectrically-conductive formations and said electrically-conductive viasprovided by applying laser beam processing to said substrate.

In a method as exemplified herein, said forming electrically-conductivematerial may comprise electroless and/or electrolytic growth (forinstance, electroless plus electrolytic) of electrically-conductivematerial, such as metal like copper.

A method as exemplified herein may comprise forming plated contactformations (see, for instance P; 12′, 1400 in FIG. 1G) over said firstpattern of electrically-conductive formations and/or said second patternof electrically-conductive formations (optionally, as exemplified inFIG. 1G, this may occur “on top” of, that is onto, theelectrically-conductive material formed as exemplified in FIG. 1F).

A method as exemplified herein may comprise:

-   -   providing a strip-like laminar substrate (see, for instance,        FIGS. 2 and 3 ) of laser direct structuring material and        applying laser beam processing to said strip-like laminar        substrate to provide a plurality of assemblies each including a        first pattern of electrically-conductive formations at the first        surface of said substrate, a second pattern of        electrically-conductive formations at the second surface of said        substrate, and electrically-conductive vias through said        substrate between the first surface of said substrate and the        second surface of said substrate, the electrically-conductive        vias coupled to at least one (see 12, 14 in FIGS. 1D to 1F and        1400 ′ in FIG. 5 , where 1400′ are coupled only to 12 on the        bottom of back side) of the electrically-conductive formations        in said first pattern of electrically-conductive formations and        said second pattern of electrically-conductive formations; and    -   applying singulation (for instance, S in FIG. 5 ) to said        strip-like laminar substrate after application of laser beam        processing, said singulation to separate the assemblies in said        plurality of assemblies.

A method as exemplified herein may comprise providing, optionally bylaser beam drilling of said strip-like laminar substrate, indexingapertures (for instance, 18) sidewise of said strip-like laminarsubstrate, said indexing apertures providing reference markers inapplying singulation to said strip-like laminar substrate.

A leadframe for semiconductor devices as exemplified herein maycomprise:

-   -   a laminar substrate of laser direct structuring material, the        laminar substrate comprising first and second opposed surfaces;        and    -   portions (for instance, 12, 120, 14, 140, 16) of said substrate        subjected to laser beam processing as exemplified herein.

A leadframe for semiconductor devices as exemplified herein may compriseelectrically-conductive material, optionally metal such as copper,formed onto said portions of said substrate subjected to laser beamprocessing.

A leadframe for semiconductor devices as exemplified herein may compriseplated contact formations over said first pattern ofelectrically-conductive formations and/or said second pattern ofelectrically-conductive formations (optionally, as exemplified in FIG.1G, these plated contact formations may be provided “on top” of, that isonto, the electrically-conductive material formed onto the portions ofthe substrate subjected to laser beam processing as exemplified in FIG.1F).

In a leadframe for semiconductor devices as exemplified herein, at leastone of said first and second pattern of electrically-conductiveformations may comprise an array of electrically-conductive formationsbetween a die-mounting area (for instance, C) of said substrate and theperiphery of said substrate.

In a leadframe for semiconductor devices as exemplified herein, saidarray of electrically-conductive formations may compriseelectrically-conductive formations having an increasing width away fromsaid die-mounting area and towards the periphery of said substrate.

A semiconductor device as exemplified herein may comprise:

-   -   one (or more) leadframe(s) as exemplified herein; and    -   one (or more) semiconductor chip(s) or die/dice (for        instance, C) attached to said leadframe, the at least one        semiconductor chip or die electrically coupled to        electrically-conductive formations out of said first pattern of        electrically-conductive formations at the first surface of said        substrate, said second pattern of electrically-conductive        formations at the second surface of said substrate and said        electrically-conductive vias.

Without prejudice to the underlying principles, the details andembodiments may vary, even significantly, with respect to what has beendescribed by way of example only, without departing from the extent ofprotection.

The various embodiments described above can be combined to providefurther embodiments. These and other changes can be made to theembodiments in light of the above-detailed description. In general, inthe following claims, the terms used should not be construed to limitthe claims to the specific embodiments disclosed in the specificationand the claims, but should be construed to include all possibleembodiments along with the full scope of equivalents to which suchclaims are entitled. Accordingly, the claims are not limited by thedisclosure.

1. A leadframe for semiconductor devices, the leadframe comprising: alaminar substrate of laser direct structuring material, the laminarsubstrate having first and second opposed surfaces; a first pattern ofelectrically-conductive structures at the first surface of thesubstrate, the first pattern of electrically-conductive structuresformed by laser beam processing; a second pattern ofelectrically-conductive structures at the second surface of thesubstrate, the second pattern of electrically-conductive structuresformed by laser beam processing; and electrically-conductive viasextending through the substrate between the first surface of thesubstrate and the second surface of the substrate, theelectrically-conductive vias coupled to at least one of theelectrically-conductive structures in the first pattern ofelectrically-conductive structures and in the second pattern ofelectrically-conductive structures.
 2. The leadframe of claim 1,comprising an electrically-conductive material on the first pattern ofelectrically-conductive structures, the second pattern ofelectrically-conductive structures, and the electrically-conductivevias.
 3. The leadframe of claim 2 wherein the electrically-conductivematerial includes copper.
 4. The leadframe of claim 1, comprising platedcontact formations over at least one of the first pattern ofelectrically-conductive formations or the second pattern ofelectrically-conductive formations.
 5. The leadframe of claim 1 whereinat least one of the first or second patterns of electrically-conductiveformations includes an array of electrically-conductive formationsbetween a die-mounting area of the substrate and the periphery of thesubstrate.
 6. The leadframe of claim 5 wherein the array ofelectrically-conductive formations includes electrically-conductiveformations having an increasing width away from the die-mounting areaand towards the periphery of the substrate.
 7. A semiconductor device,comprising: a leadframe, including: a laminar substrate of laser directstructuring material, the laminar substrate having first and secondopposed surfaces; a first pattern of electrically-conductive structuresat the first surface of the substrate, the first pattern ofelectrically-conductive structures formed by laser beam processing; asecond pattern of electrically-conductive structures at the secondsurface of the substrate, the second pattern of electrically-conductivestructures formed by laser beam processing; and electrically-conductivevias extending through the substrate between the first surface of thesubstrate and the second surface of the substrate, theelectrically-conductive vias coupled to at least one of theelectrically-conductive structures in the first pattern ofelectrically-conductive structures and in the second pattern ofelectrically-conductive structures; and at least one semiconductor chipor die attached to the leadframe, the at least one semiconductor chip ordie electrically coupled to the first pattern of electrically-conductiveformations at the first surface of the substrate, the second pattern ofelectrically-conductive formations at the second surface of thesubstrate and the electrically-conductive vias.
 8. The semiconductordevice of claim 7, comprising an electrically-conductive material on thefirst pattern of electrically-conductive structures, the second patternof electrically-conductive structures, and the electrically-conductivevias.
 9. The semiconductor device of claim 8 wherein theelectrically-conductive material includes copper.
 10. The semiconductordevice of claim 7, comprising plated contact formations over at leastone of the first pattern of electrically-conductive formations or thesecond pattern of electrically-conductive formations.
 11. Thesemiconductor device of claim 7 wherein at least one of the first orsecond patterns of electrically-conductive formations includes an arrayof electrically-conductive formations between a die-mounting area of thesubstrate and the periphery of the substrate.
 12. The semiconductordevice of claim 11 wherein the array of electrically-conductiveformations includes electrically-conductive formations having anincreasing width away from the die-mounting area and towards theperiphery of the substrate.
 13. A device, comprising: a substrate; afirst pattern of laser direct structuring electrically-conductivestructures on a first side of the substrate; a second pattern of laserdirect structuring electrically-conductive structures on a second sideof the substrate; a plurality of vias coupled between the first andsecond patterns of electrically-conductive structures.
 14. The device ofclaim 13 wherein the substrate is a laminate core.
 15. The device ofclaim 13 wherein the substrate is a laser direct structuring material.16. The device of claim 13 wherein the first pattern is a firstplurality of contact pads around a die pad area.
 17. The device of claim16 wherein the second pattern is a second plurality of contact pads thatcorresponds and is aligned with the first plurality of contact pads.